1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a silicon germanium (SiGe) epitaxial structure.
2. Description of the Prior Art
With the trend in the industry being scaling down the size of the field effect transistors (FETs), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar FETs. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect (SCE) are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased.
However, layout designs of the FinFET structures still face some issues in conventional FinFET fabrication. Hence, how to improve the current FinFET fabrication and structure for resolving such issue has become an important task in this field.